1. Field of the Invention
The present invention relates to a single poly EEPROM device, and more particularly, to a single poly EEPROM device which can reduce the size of a single poly EEPROM cell, that is, an element of the single poly EEPROM device, without deteriorating characteristics and reduce the number of MOS devices used therein.
2. Description of the Related Art
An RFID is radio frequency recognition technology that provides various services by collecting, storing, modifying, and tracking information about objects and peripheral information using radio waves from tags attached to the objects. A tag chip includes an analog circuit, a logic circuit, and a memory IP. EEPROM, that is, non-volatile memory capable of being read and written and retaining stored information although power is not supplied, is chiefly used as the memory IP. There is a need for an EEPROM IP using a single poly EEPROM cell having a small area in order to reduce the cost of a tag chip.
A conventional single poly EEPROM cell does not use an additional mask or uses one additional mask in a common CMOS process, has a small size, and uses a Fowler Nordheim (FN) tunneling method having a lower current than a Channel Hot Electron (CHE) method or a Band To Band Tunneling (BTBT) method in erase mode and program mode. The FN tunneling method is a quantum tunnel effect and a method of electrically rewriting data using FN tunneling. A single poly EEPROM device is used for an RFID tag chip because a small additional mask, a short Turn Around Time (TAT), and a low manufacturing cost.
A conventional single poly EEPROM cell includes a control gate capacitor, a tunnel gate capacitor, a sense transistor, and a selection transistor. The sense transistor and the selection transistor are problematic in that they occupy a large area because the transistor is formed in each well process.